`timescale 1ns/1ns
module testbench();

reg CCLK;
reg ROTCTR;
reg BTN0;
wire SPIMISO;
wire SPISCK;
wire SPIMOSI;
wire SFCE;
wire SPISF;
wire FPGAIB;
wire AMPCS;
wire DACCS;
wire ADCON;
wire LCDE;
wire LCDRS;
wire LCDRW;
wire [3:0] LCDDAT; 
wire [7:0] LED;
reg  ROTA;
reg  ROTB;

// gui use
wire [7:0]  char_out;
wire        row_out;
wire [3:0]  column_out;
wire        char_valid;

// counter variable
reg [63:0] i;

lcd_control LCD_CTRL(
  .lcddat(LCDDAT),
  .lcdrs(LCDRS),
  .lcdrw(LCDRW),
  .lcde(LCDE),
  .char_out(char_out),
  .row_out(row_out),
  .column_out(column_out),
  .char_valid(char_valid)
  );

command CMD(
  .CCLK(CCLK),
  .BTN0(BTN0),
  //.SPIMISO(SPIMISO),
  .SPISCK(SPISCK),
  .SPIMOSI(SPIMOSI),
  .SFCE(SFCE),
  .SPISF(SPISF),
  .FPGAIB(FPGAIB),
  .AMPCS(AMPCS),
  .DACCS(DACCS),
  .ADCON(ADCON),
  .LCDE(LCDE),
  .LCDRS(LCDRS),
  .LCDRW(LCDRW),
  .LCDDAT(LCDDAT),
  .ROTA(ROTA),
  .ROTB(ROTB),
  .rotary_pushbtn(ROTCTR),
  .LED(LED)
);

always begin
  #5 CCLK = ~CCLK;
  end
  
initial begin
  CCLK = 1'b0;
  BTN0 = 1'b0;
  ROTA = 1'b1;
  ROTB = 1'b1;
  ROTCTR = 1'b0;
  i = 1'b0;
  @(negedge CCLK);
  @(negedge CCLK);
  
  
  //reset
  BTN0 = 1'b1;
  @(negedge CCLK);
  @(negedge CCLK);
  BTN0 = 1'b0;
  for(i = 0; i<64'hcebbb; i = i+1) begin
  @(negedge CCLK);
  end
  
  ROTCTR = 1'b1;
  for(i = 0; i<4'hF; i = i+1) begin
  @(negedge CCLK);
  end
  ROTCTR = 1'b0;
  for(i = 0; i<4'hF; i = i+1) begin
  @(negedge CCLK);
  end
  
  ROTCTR = 1'b1;
  for(i = 0; i<4'hF; i = i+1) begin
  @(negedge CCLK);
  end
  ROTCTR = 1'b0;
  for(i = 0; i<4'hF; i = i+1) begin
  @(negedge CCLK);
  end
  
  
  //////clockwise turn
  ROTA = 1'b0;
  for(i = 0; i<64'h8; i = i+1) begin
  @(negedge CCLK);
  end
  ROTB = 1'b0;
  for(i = 0; i<64'h8; i = i+1) begin
  @(negedge CCLK);
  end
  ROTA = 1'b1;
  for(i = 0; i<64'h8; i = i+1) begin
  @(negedge CCLK);
  end  
  ROTB = 1'b1;
  for(i = 0; i<64'h8; i = i+1) begin
  @(negedge CCLK);
  end
  
  ////////wait for 0x25000 clocks
  // for(i = 0; i<64'h25000; i = i+1) begin
  // @(negedge CCLK);
  // end
  
  ////////counterclockwise turn
  // ROTB = 1'b0;
  // for(i = 0; i<64'h20; i = i+1) begin
  // @(negedge CCLK);
  // end
  // ROTA = 1'b0;
  // for(i = 0; i<64'h20; i = i+1) begin
  // @(negedge CCLK);
  // end
  // ROTB = 1'b1;
  // for(i = 0; i<64'h20; i = i+1) begin
  // @(negedge CCLK);
  // end  
  // ROTA = 1'b1;
  // for(i = 0; i<64'h50; i = i+1) begin
  // @(negedge CCLK);
  // end 

  
end

endmodule